cbadc.circuit.testbench.LCTestBench
===================================

.. currentmodule:: cbadc.circuit.testbench

.. autoclass:: LCTestBench
   :members:
   :show-inheritance:
   :inherited-members:

   


   
   .. rubric:: Methods

   .. autosummary::
   
      ~LCTestBench.__init__
      ~LCTestBench.add
      ~LCTestBench.add_terminal
      ~LCTestBench.add_terminals
      ~LCTestBench.check_connections
      ~LCTestBench.check_subckt_names
      ~LCTestBench.connect
      ~LCTestBench.connect_upstream
      ~LCTestBench.connects
      ~LCTestBench.get_ngspice
      ~LCTestBench.get_spectre
      ~LCTestBench.get_sub_circuit_definitions
      ~LCTestBench.get_terminals
   
   

   
   
   .. rubric:: Attributes

   .. autosummary::
   
      ~LCTestBench.title
      ~LCTestBench.Xaf
      ~LCTestBench.input_signals
      ~LCTestBench.highlighted_terminals
      ~LCTestBench.Vss
      ~LCTestBench.Vdd
      ~LCTestBench.Vclk
      ~LCTestBench.verilog_ams_library_name
      ~LCTestBench.Aobs
      ~LCTestBench.subckt_name
      ~LCTestBench.instance_name
      ~LCTestBench.comments
      ~LCTestBench.model
   
   

.. _sphx_glr_backref_cbadc.circuit.testbench.LCTestBench: