cbadc.circuit.testbench.TestBench
=================================

.. currentmodule:: cbadc.circuit.testbench

.. autoclass:: TestBench
   :members:
   :show-inheritance:
   :inherited-members:

   


   
   .. rubric:: Methods

   .. autosummary::
   
      ~TestBench.__init__
      ~TestBench.add
      ~TestBench.add_terminal
      ~TestBench.add_terminals
      ~TestBench.check_connections
      ~TestBench.check_subckt_names
      ~TestBench.connect
      ~TestBench.connect_upstream
      ~TestBench.connects
      ~TestBench.get_ngspice
      ~TestBench.get_spectre
      ~TestBench.get_sub_circuit_definitions
      ~TestBench.get_terminals
   
   

   
   
   .. rubric:: Attributes

   .. autosummary::
   
      ~TestBench.title
      ~TestBench.Xaf
      ~TestBench.input_signals
      ~TestBench.highlighted_terminals
      ~TestBench.Vss
      ~TestBench.Vdd
      ~TestBench.Vclk
      ~TestBench.verilog_ams_library_name
      ~TestBench.Aobs
      ~TestBench.subckt_name
      ~TestBench.instance_name
      ~TestBench.comments
      ~TestBench.model
   
   

.. _sphx_glr_backref_cbadc.circuit.testbench.TestBench: